ath9k: do not track cycle counter updates in powersave mode
authorFelix Fietkau <nbd@openwrt.org>
Tue, 12 Oct 2010 12:02:53 +0000 (14:02 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 15 Oct 2010 19:48:44 +0000 (15:48 -0400)
commit898c914a0871ea7e5557b77156d4358c0f15d98a
tree7c3fb4a99f3a0f6154b7f52a20f21b3ea9e61597
parent3be63ff0ae196b371728ba8fc8aca12eafcae218
ath9k: do not track cycle counter updates in powersave mode

While the chip is in powersave mode, the cycle counter updates do not
contain useful values. While the chip is in full sleep, the rx_clear
signal stays high, indicating a busy medium.
To ensure sane values, update cycle counters before going into
powersave, and clear them right after switching back to awake.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/main.c