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iio: adc: ti-ads8344: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:56:17 +0000 (18:56 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:15 +0000 (11:53 +0100)
commit8966b11e5a14aaabc747ee97a7942fd50a681402
tree6100050194f387d70807de5c4e2e752020c1520etree | snapshot
parentdd54ba8b2469f6ae665c529623a9454ce5293ca8commit | diff
iio: adc: ti-ads8344: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-38-jic23@kernel.org
drivers/iio/adc/ti-ads8344.c diff | blob | history
Domain: System / Kernel;