[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel...
authorCraig Topper <craig.topper@sifive.com>
Sat, 25 Feb 2023 17:57:57 +0000 (09:57 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sat, 25 Feb 2023 17:57:57 +0000 (09:57 -0800)
commit893428767cbef85b0c729d3f0d36ab717c950bcf
tree2a9cc3737a674f9fbf3ca98eb734c0d66fa81eed
parent3d4b7a6fa8a45488c141a8640cd53980bdb868e5
[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td