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ARM: at91: pm: add sama7g5 ddr phy controller
authorClaudiu Beznea <claudiu.beznea@microchip.com>
Thu, 15 Apr 2021 10:50:04 +0000 (13:50 +0300)
committerNicolas Ferre <nicolas.ferre@microchip.com>
Mon, 19 Jul 2021 12:32:12 +0000 (14:32 +0200)
commit892e1f4a3ae58c1cd376d952d45dca6f20dc712c
treef6de9f1e138eb48423937d2ceb3067d3234ad7cetree | snapshot
parent2c26cb4d6944edf0a65a4b1fdeacdcc816261739commit | diff
ARM: at91: pm: add sama7g5 ddr phy controller

SAMA7G5 self-refresh procedure accesses also the DDR PHY registers.
Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs,
in case it is mandatory.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
arch/arm/mach-at91/pm.c diff | blob | history
Domain: System / Kernel;