[AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions
authorDavid Sherwood <david.sherwood@arm.com>
Tue, 25 Oct 2022 11:06:51 +0000 (11:06 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Thu, 27 Oct 2022 18:23:35 +0000 (18:23 +0000)
commit891aaff9a8a9997582eac1bb1edb8d4b4e117ef1
tree407d584c4f2d03231d956f8e9d8aaa936a78cfae
parent80b08b68f219949a6479aeff6a54e3e5129ce7dc
[AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

This patch adds the assembly/disassembly for the following instructions:

pext (predicate) : Set predicate from predicate-as-counter
ptrue (predicate-as-counter) : Initialise predicate-as-counter to all active

This patch also introduces the predicate-as-counter registers pn8, etc.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136678
15 files changed:
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s [new file with mode: 0644]
llvm/test/MC/AArch64/SVE2p1/pext.s [new file with mode: 0644]
llvm/test/MC/AArch64/SVE2p1/ptrue-diagnostics.s [new file with mode: 0644]
llvm/test/MC/AArch64/SVE2p1/ptrue.s [new file with mode: 0644]