[AMDGPU] Increased vector length for global/constant loads.
authorFarhana Aleen <farhana.aleen@gmail.com>
Wed, 7 Mar 2018 17:09:18 +0000 (17:09 +0000)
committerFarhana Aleen <farhana.aleen@gmail.com>
Wed, 7 Mar 2018 17:09:18 +0000 (17:09 +0000)
commit89196642f72cc3325963918c0426ce128c414104
tree1c0fb19b4dcb115932854c6cfc86768b38a5e136
parentc0e768df9050133466695f3a8f3bf0b3bb343987
[AMDGPU] Increased vector length for global/constant loads.

Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache;
         loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.

Author: FarhanaAleen

Reviewed By: rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D44179

llvm-svn: 326910
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
llvm/test/CodeGen/AMDGPU/load-constant-f32.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
llvm/test/CodeGen/AMDGPU/waitcnt-looptest.ll