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[AArch64][SME2] Add multi-vector FP convert from Float to interleave Half/BFloat...
authorCaroline Concatto <caroline.concatto@arm.com>
Fri, 20 Jan 2023 17:14:16 +0000 (17:14 +0000)
committerCaroline Concatto <caroline.concatto@arm.com>
Fri, 20 Jan 2023 17:44:53 +0000 (17:44 +0000)
commit88fd2e4cb59cdea37cf572e8eb79fbaf73a47178
treecef83c8a633c0c4adc124f2a9f8152c1d2c2e106tree | snapshot
parent86eff6be686a1e41e13c08ebfc2db4dd4d58e7c6commit | diff
[AArch64][SME2] Add multi-vector FP convert from Float to interleave Half/BFloat intrinsic

Add the following intrinsic:
  FCVTN
  BFCVTN

NOTE: These intrinsics are still in development and are subject to future changes.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D142025
llvm/include/llvm/IR/IntrinsicsAArch64.td diff | blob | history
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td diff | blob | history
llvm/lib/Target/AArch64/SMEInstrFormats.td diff | blob | history
llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll [new file with mode: 0644] blob
Domain: System / Toolchain;