[DAGCombine]Expand usage of CreateBuildVecShuffle to make full use of vector ops
authorWang, Xin10 <xin10.wang@intel.com>
Mon, 23 Jan 2023 02:37:26 +0000 (10:37 +0800)
committerPhoebe Wang <phoebe.wang@intel.com>
Mon, 23 Jan 2023 03:45:38 +0000 (11:45 +0800)
commit88eae6ef9fb527bfd979c1672e2ed07f77136fbd
tree39933fbb40b7f988f2849a77f090734f7dbba8b7
parent8ab77a78ba059c0f5f357d7b1062b25b5ab0cb61
[DAGCombine]Expand usage of CreateBuildVecShuffle to make full use of vector ops

Now, when llc encounters the case that contains a lot of
extract_vector_elt and a BUILD_VECTOR, it will replace these to
vector_shuffle to decrease the size of code, the actions are done in
createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle
the case that the size of source vector reg is more than twice the dest
size.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D139685
15 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/pr29112.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll