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(parent: 60c9b41) | patch
assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
authorZhao Yakui <yakui.zhao@intel.com>
Tue, 9 Apr 2013 01:59:15 +0000 (09:59 +0800)
committerBen Widawsky <benjamin.widawsky@intel.com>
Wed, 6 Nov 2013 17:39:41 +0000 (09:39 -0800)
commit88e5f1fdf847a0ce284b8a01ff2cf3fb36e2b07c
tree663ad36560500c38ec4ebb2cdfca2f7359d8fc02tree | snapshot
parent60c9b41e11bf4a3ea4935bd30f5c169ca24de06dcommit | diff
assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
assembler/gen8_instruction.c diff | blob | history
assembler/gen8_instruction.h diff | blob | history
assembler/gram.y diff | blob | history
Domain: SCM / Uncategorized;