[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 21 Jul 2016 14:54:17 +0000 (14:54 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 21 Jul 2016 14:54:17 +0000 (14:54 +0000)
commit88e0940d3bde4bf5c2a2997895830f4826174fd2
treeaeaf06e123b72728b11273056def0ee75f839df3
parent5ad891f7193b2d7cc6578c2cbffe7d3a04e4617b
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element

Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW.

But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register.

This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41).

Fix for PR27265.

Differential Revision: https://reviews.llvm.org/D22509

llvm-svn: 276289
18 files changed:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/2011-12-8-bitcastintprom.ll
llvm/test/CodeGen/X86/avx512-trunc.ll
llvm/test/CodeGen/X86/extract-store.ll
llvm/test/CodeGen/X86/lower-vec-shift-2.ll
llvm/test/CodeGen/X86/masked_memop.ll
llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
llvm/test/CodeGen/X86/vector-shift-shl-128.ll
llvm/test/CodeGen/X86/vector-shift-shl-256.ll
llvm/test/CodeGen/X86/vector-shift-shl-512.ll
llvm/test/CodeGen/X86/widen_conv-1.ll
llvm/test/CodeGen/X86/widen_load-2.ll