review.tizen.org Git - platform/upstream/llvm.git/commit

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author	Jay Foad <jay.foad@amd.com>
	Mon, 27 Jun 2022 11:15:25 +0000 (12:15 +0100)
committer	Jay Foad <jay.foad@amd.com>
	Mon, 27 Jun 2022 11:15:29 +0000 (12:15 +0100)
commit	8871c3c562690347d75190be758312d1f92a7db4
tree	5952d94d65c58472babe34799061114fa2bb0cdb	tree \| snapshot
parent	4588b6fd266243eaa0d970d34fd4e11e4082cd1e	commit \| diff

[AMDGPU] Regenerate MIR checks. NFC.

573 files changed:

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir		diff \| blob \| history
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