phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Wed, 2 Nov 2022 08:18:35 +0000 (13:48 +0530)
committerVinod Koul <vkoul@kernel.org>
Thu, 10 Nov 2022 07:15:46 +0000 (12:45 +0530)
commit883aebf6e1ea88145d64dcf940dbcb5181313338
treebcfa8821ebd18443e1c1956b53df1e57b5896d15
parent9ddcd920f8edfe65c3670fbd0b49db00e1e562fe
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names

sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.

Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h [new file with mode: 0644]
drivers/phy/qualcomm/phy-qcom-qmp.h