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(parent: 1f3e84c) | patch
drm/i915/dg2: Skip shared DPLL handling
authorMatt Roper <matthew.d.roper@intel.com>
Wed, 21 Jul 2021 22:30:37 +0000 (15:30 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 22 Jul 2021 16:29:20 +0000 (09:29 -0700)
commit87fc875a2b85043f9cc34f84e1beb2ec51a9e5d3
tree0b23f9cc9d898bb0dfcb822182494a459f5cf643tree | snapshot
parent1f3e84c4edcd357eeb608d709c9c2dcb3193c841commit | diff
drm/i915/dg2: Skip shared DPLL handling

DG2 has no shared DPLL's or DDI clock muxing.  The Port PLL is embedded
within the PHY.

Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-13-matthew.d.roper@intel.com
drivers/gpu/drm/i915/display/intel_display.c diff | blob | history
drivers/gpu/drm/i915/display/intel_dpll_mgr.c diff | blob | history
Domain: System / Kernel;