clk: at91: fix recalc_rate implementation of PLL driver
authorBoris BREZILLON <boris.brezillon@free-electrons.com>
Tue, 2 Sep 2014 07:50:16 +0000 (09:50 +0200)
committerMike Turquette <mturquette@linaro.org>
Tue, 2 Sep 2014 22:37:17 +0000 (15:37 -0700)
commit87e2ed338f1b56798807ccf12eb6112d25062202
tree3547acba47040ac108b4ecb02a3c414aa1ed1ada
parent3ef9dd2bab7d6a013f75f9fb226d0191e9981288
clk: at91: fix recalc_rate implementation of PLL driver

Use the cached values to calculate PLL rate instead of the register values.
This is required to prevent erroneous PLL rate return when the PLL rate
has been configured but the PLL is not prepared yet.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/at91/clk-pll.c