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riscv: dts: starfive - Add hwrng node for JH7110 SoC
authorJia Jie Ho <jiajie.ho@starfivetech.com>
Tue, 8 Aug 2023 14:15:58 +0000 (22:15 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 9 Aug 2023 18:43:51 +0000 (19:43 +0100)
commit87ddf5b1096467d24584ea61de0580776722d961
tree326f27454bfed3f3e936e72416c3241d75cf6208tree | snapshot
parente2c07765e179d0849326d4e1bd62ef8ba3d3cfd1commit | diff
riscv: dts: starfive - Add hwrng node for JH7110 SoC

Add hardware rng controller node for StarFive JH7110 SoC.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
Domain: System / Kernel;