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(parent: 94eca90) | patch
spi: lantiq: Add fifo size bit mask in SoC specific data structure
authorDilip Kota <eswara.kota@linux.intel.com>
Fri, 17 Jul 2020 06:27:54 +0000 (14:27 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 22 Jul 2020 00:55:57 +0000 (01:55 +0100)
commit8743d2155aed9236202294e293ab13d33b3a7682
tree012e47018031f1412ca26d67126add81d684a0d6tree | snapshot
parent94eca904cb97f9cfa90e3e558fb73c49d2e42f91commit | diff
spi: lantiq: Add fifo size bit mask in SoC specific data structure

On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/a0889abf17a9fbc7077f10be0f0342b7ebdf9361.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-lantiq-ssc.c diff | blob | history
Domain: System / Kernel;