clk:starfive:vout:Add parent about disp_apb clk
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 8 Nov 2022 13:53:31 +0000 (21:53 +0800)
committershengyang.chen <shengyang.chen@starfivetech.com>
Mon, 14 Nov 2022 06:53:42 +0000 (14:53 +0800)
commit873c005ea02384c72766e7b2f2ab87a6c374176f
tree2919b31bce4d94716da72b23144c2b826efe0b8a
parent21b8e810427d489ab78b756b6ef85b2fb55ec052
clk:starfive:vout:Add parent about disp_apb clk

Clock "u0_pclk_mux_func_pclk" is the parent of "disp_apb" clock.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-vout.c