[PATCH, rs6000] int128 sign extention instructions (partial prereq)
authorWill Schmidt <will_schmidt@vnet.ibm.com>
Thu, 17 Sep 2020 22:17:15 +0000 (17:17 -0500)
committerWill Schmidt <will_schmidt@vnet.ibm.com>
Thu, 22 Oct 2020 14:42:52 +0000 (09:42 -0500)
commit8732511910e1dd23c56c01e876bbe235c360ac55
treeb56f03f767618c10be8237c9dbe95d37ae42a250
parentdfb7345cd54e90b4f5cc0234bd37ec2763602180
[PATCH, rs6000] int128 sign extention instructions (partial prereq)

Hi
  This is a sub-set of the 128-bit sign extension support patch series
  that will be fully implemented in a subsequent patch from Carl.
  This is a necessary pre-requisite for the vector-load/store rightmost
  element patch that follows in this thread.

  [v2] Refreshed and touched up per review comments.
  - updated set_attr entries.  removed superfluous set_attr entries.
  - moved define_insn and define_expand entries to vsx.md.

gcc/ChangeLog:
* config/rs6000/vsx.md (enum unspec): Add
UNSPEC_EXTENDDITI2 and UNSPEC_MTVSRD_DITI_W1 entries.
(mtvsrdd_diti_w1, extendditi2_vector): New define_insns.
(extendditi2): New define_expand.
gcc/config/rs6000/vsx.md