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author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 7 Aug 2017 14:58:04 +0000 (14:58 +0000)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 7 Aug 2017 14:58:04 +0000 (14:58 +0000)
commit	8728c5f2db48be88952db24213d62825ca04264b
tree	e15526659c28fb0b488e96cd71fcaf954d159cab	tree \| snapshot
parent	53d523c9eb1fba3714d39802fef27eb75ed35baa	commit \| diff

AMDGPU: Cleanup subtarget features

Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.

Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.

llvm-svn: 310258

72 files changed:

llvm/lib/Target/AMDGPU/AMDGPU.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/FLATInstructions.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/Processors.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/addrspacecast.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/br_cc.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/captured-frame-index.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ctpop64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fabs.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fadd.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fence-amdgiz.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmax3.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmul.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fpext.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fptosi.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fptoui.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/frame-index-amdgiz.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fsub.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/half.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.exp2.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.log2.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.round.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-stores.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/s_addk_i32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sad.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/select-vectors.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/select.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shl_add_constant.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sitofp.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/trunc.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/udivrem.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/uitofp.f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/v_mac_f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll		diff \| blob \| history

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