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[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors
authorLemonBoy <thatlemon@gmail.com>
Fri, 5 Mar 2021 15:01:45 +0000 (16:01 +0100)
committerLemonBoy <thatlemon@gmail.com>
Fri, 5 Mar 2021 15:09:37 +0000 (16:09 +0100)
commit8725b24c6d4abaa97425e704652a13dacb35fe3f
tree82e28d2653b63d55eb6715c81f4bd769bbd35175tree | snapshot
parent5fedf30748381ad84697291591dab7d570f50d06commit | diff
[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49401

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D97840
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll diff | blob | history
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll diff | blob | history
Domain: System / Toolchain;