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(parent: fc03aca) | patch
irqchip/sifive-plic: Pre-compute context hart base and enable base
authorAnup Patel <anup@brainfault.org>
Tue, 12 Feb 2019 12:52:43 +0000 (18:22 +0530)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 21 Feb 2019 10:32:05 +0000 (10:32 +0000)
commit86c7cbf1e8d1d4f4f60e229fdc2a5b21c09c29a3
treea7d4426654e3b0b8b6f0930b668beec8a3d1042btree | snapshot
parentfc03acaeab358c008a194b78daa10e78401376a8commit | diff
irqchip/sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations:
1. Pre-compute hart base for each context handler
2. Pre-compute enable base for each context handler
3. Have enable lock for each context handler instead
of global plic_toggle_lock

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
drivers/irqchip/irq-sifive-plic.c diff | blob | history
Domain: System / Kernel;