[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt
authorJessica Paquette <jpaquette@apple.com>
Fri, 19 Feb 2021 17:25:31 +0000 (09:25 -0800)
committerJessica Paquette <jpaquette@apple.com>
Mon, 22 Feb 2021 22:44:09 +0000 (14:44 -0800)
commit867e379c0e14527eb7aa68485a10324693e35f5d
tree122814bf4d5d76a1bbaa3b7b1097abfeaee31662
parent89440df64a5bf9981111e5980647e958f132b6a9
[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt

Match a G_SHUFFLE_VECTOR with a mask that allows it to be represented as a
G_INSERT_VECTOR_ELT and a G_EXTRACT_VECTOR_ELT.

This ports `isINSMask` from AArch64ISelLowering and the portion of
`AArch64TargetLowering::LowerVECTOR_SHUFFLE` which handles the equivalent
transformation.

This provides more opportunities for matching DUP. We don't have all of the
necessary combines to actually make DUP out of these yet, but this is better for
size than the full TBL expansion for G_SHUFFLE_VECTOR.

This is a -0.1% code size improvement on CTMark/Bullet at -Os.

IR example: https://godbolt.org/z/sdcevT

Differential Revision: https://reviews.llvm.org/D97214
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir [new file with mode: 0644]