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(parent: 80c0a06) | patch
clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL
authorChanwoo Choi <cw00.choi@samsung.com>
Tue, 29 Dec 2015 01:42:39 +0000 (10:42 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 14 Dec 2016 04:50:37 +0000 (13:50 +0900)
commit8678861ee4325e601154b1d4658a2bd9964ea05b
treee6b9aadc0ae2c8e53b95054c6c3f12a3bfc594ectree | snapshot
parent80c0a067818a14f016f4bb450ac794a06520fad3commit | diff
clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL

This patch add the clock id of EPLL to handle it on devicetree file
and the rate tables. EPLL is used as root clock of ASS (Audio Subsystem).

Change-Id: Iefcbd5ea4cb911a3b5d75888286926773a98af54
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
include/dt-bindings/clock/exynos5420.h diff | blob | history
Domain: System / Kernel;