arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
authorAndrew Murray <andrew.murray@arm.com>
Mon, 2 Mar 2020 18:17:52 +0000 (18:17 +0000)
committerWill Deacon <will@kernel.org>
Tue, 17 Mar 2020 22:50:30 +0000 (22:50 +0000)
commit8673e02e58410e6c4cefa499efa846286e45a991
tree60273aa60c2777d8a4dea7d56951f545731d2cfe
parentc854188ea01062f5a5fd7f05658feb1863774eaa
arm64: perf: Add support for ARMv8.5-PMU 64-bit counters

At present ARMv8 event counters are limited to 32-bits, though by
using the CHAIN event it's possible to combine adjacent counters to
achieve 64-bits. The perf config1:0 bit can be set to use such a
configuration.

With the introduction of ARMv8.5-PMU support, all event counters can
now be used as 64-bit counters.

Let's enable 64-bit event counters where support exists. Unless the
user sets config1:0 we will adjust the counter value such that it
overflows upon 32-bit overflow. This follows the same behaviour as
the cycle counter which has always been (and remains) 64-bits.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Mark: fix ID field names, compare with 8.5 value]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
arch/arm64/include/asm/perf_event.h
arch/arm64/include/asm/sysreg.h
arch/arm64/kernel/perf_event.c
include/linux/perf/arm_pmu.h