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re PR target/78862 (tile*: ICE with -fstack-protetor-strong)
authorWalter Lee <walt@tilera.com>
Fri, 3 Feb 2017 18:41:57 +0000 (18:41 +0000)
committerWalter Lee <walt@gcc.gnu.org>
Fri, 3 Feb 2017 18:41:57 +0000 (18:41 +0000)
commit86010a086b6ae8f1b129b6e992ed2ce2a36e38e3
treeee31af49185c9ceec99bcc3ee41eddd3a7825aeftree | snapshot
parentd9327911bfb074734d2293c9ff0698b1197b0563commit | diff
re PR target/78862 (tile*: ICE with -fstack-protetor-strong)

PR target/78862
* config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
after initial stackframe link reg save.
* config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.

From-SVN: r245159
gcc/ChangeLog diff | blob | history
gcc/config/tilegx/tilegx.c diff | blob | history
gcc/config/tilepro/tilepro.c diff | blob | history
Domain: System / Toolchain;