[ARM] Fix sema check of ARM special register names

[ARM] Fix sema check of ARM special register names

Summary:
This is a simple sema check patch for arguments of `__builtin_arm_rsr` and the related builtins, which currently do not allow special registers with indexes >7.

Some of the possible register name formats these builtins accept are:
```
{c}p<coprocessor>:<op1>:c<CRn>:c<CRm>:<op2>
```
```
o0:op1:CRn:CRm:op2
```
where `op1` / `op2` are integers in the range [0, 7] and `CRn` / `CRm` are integers in the range [0, 15].

The current sema check does not allow `CRn` > 7 and accepts `op2` up to 15.

Reviewers: LukeCheeseman, rengolin

Subscribers: asl, aemerson, rengolin, cfe-commits

Differential Revision: https://reviews.llvm.org/D26464

llvm-svn: 287378