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(parent: 3956a1f) | patch
[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sat, 16 Oct 2021 16:27:52 +0000 (17:27 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sat, 16 Oct 2021 16:28:07 +0000 (17:28 +0100)
commit85b87179f4820592894d2d1da699794edf9ad6b6
tree581cb37065cbbc5f000a05e34ee4c417244ed4bftree | snapshot
parent3956a1f8b6d29d2ed3590c7e8f877c7525b165efcommit | diff
[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs

Split SSE2 and SSSE3 costs to correctly handle PSHUFB lowering - as was noted on D111938
llvm/lib/Target/X86/X86TargetTransformInfo.cpp diff | blob | history
llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll diff | blob | history
llvm/test/Transforms/LoopVectorize/X86/pr47437.ll diff | blob | history
Domain: System / Toolchain;