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(parent: 6a84579) | patch
[RISCV] Allow PRE of vsetvli involving non-1 LMUL
authorPhilip Reames <preames@rivosinc.com>
Fri, 27 May 2022 22:37:42 +0000 (15:37 -0700)
committerPhilip Reames <listmail@philipreames.com>
Fri, 27 May 2022 22:49:41 +0000 (15:49 -0700)
commit85b4470035b74834dcba3be14e8abb530f302caa
treed1a5e9aa76bd60b6a45438e0f6a933970b6fc041tree | snapshot
parent6a8457924335623eb2303775894dbde39fcf4e64commit | diff
[RISCV] Allow PRE of vsetvli involving non-1 LMUL

This is a follow up to address a review comment from D124869. When deciding whether to PRE a vsetvli, we can allow non-LMUL1 vsetvlis.

Differential Revision: https://reviews.llvm.org/D126563
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll diff | blob | history
Domain: System / Toolchain;