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(parent: c7994bd) | patch
[RISCV] Check all 64-bits of the mask in SelectRORIW.
authorCraig Topper <craig.topper@sifive.com>
Wed, 4 Nov 2020 18:15:30 +0000 (10:15 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 4 Nov 2020 18:15:30 +0000 (10:15 -0800)
commit857563eaf02f7aa3cc3748e2c36b45ae14294bf8
tree3a26cb5afa4dbe25f428d9597f4222fd80d0b3e3tree | snapshot
parentc7994bd939f3f4af0f081a55122c7cde68154e3ccommit | diff
[RISCV] Check all 64-bits of the mask in SelectRORIW.

We need to ensure the upper 32 bits of the mask are zero.
So that the srl shifts zeroes into the lower 32 bits.

Differential Revision: https://reviews.llvm.org/D90585
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rv64Zbbp.ll diff | blob | history
Domain: System / Toolchain;