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tools/testing/cxl: Expand CFMWS windows
authorDan Williams <dan.j.williams@intel.com>
Tue, 24 May 2022 15:56:58 +0000 (08:56 -0700)
committerDan Williams <dan.j.williams@intel.com>
Sun, 10 Jul 2022 17:29:26 +0000 (10:29 -0700)
commit855c90d30575f95c5a1fb72f9294a9f75dae20c2
tree2a3b2ab05c25660230e4ce17a8d70a6ef8834b77tree | snapshot
parentb2f3b74e1072ab7c03833f265bdb26dafa92e078commit | diff
tools/testing/cxl: Expand CFMWS windows

For the x2 host-bridge interleave windows, allow for a
x8-endpoint-interleave configuration per memory-type with each device
contributing the minimum 256MB extent. Similarly, for the x1 host-bridge
interleave windows, allow for a x4-endpoint-interleave configuration per
memory-type.

Bump up the number of decoders per-port to support hosting 8 regions.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165603886721.551046.8682583835505795210.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
tools/testing/cxl/test/cxl.c diff | blob | history
Domain: System / Kernel;