AMDGPU/SI: Fix read2 merging into a super register.
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 14 Jul 2015 17:57:36 +0000 (17:57 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 14 Jul 2015 17:57:36 +0000 (17:57 +0000)
commit84db5d97b05ec4618cf931a5371662e61a45134d
tree99cd971c8ee176972229987688f90cf35ef1a8e3
parent9912bb817cef9d1829acb4baec4a27b7eaf5b610
AMDGPU/SI: Fix read2 merging into a super register.

If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

llvm-svn: 242174
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/test/CodeGen/AMDGPU/ds_read2.ll
llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
llvm/test/CodeGen/AMDGPU/ds_write2.ll
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll