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(parent: b676853) | patch
clk: renesas: r9a07g043: Add clock and reset entries for ADC
authorBiju Das <biju.das.jz@bp.renesas.com>
Sun, 1 May 2022 08:34:50 +0000 (09:34 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit84c9829d16d86a09703d9f2c8dac3816c56bcdcd
treebee90b248eadf52fb7e100352f997e602f4bb372tree | snapshot
parentb67685300478ff768bde0d06a2a664a66223945fcommit | diff
clk: renesas: r9a07g043: Add clock and reset entries for ADC

Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
Domain: System / Kernel;