[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBenefici...
authorCraig Topper <craig.topper@intel.com>
Tue, 9 Jul 2019 19:55:28 +0000 (19:55 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 9 Jul 2019 19:55:28 +0000 (19:55 +0000)
commit84a1f07363405c25304e3fd3df55a216676e9984
treeda18767d1cb035014d1b7ae007b82ca8a62e9521
parentc236eeaf7d8a95a3457c4658600ee5b79052b7a2
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it

Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.

This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.

Differential Revision: https://reviews.llvm.org/D64295

llvm-svn: 365549
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/test/CodeGen/X86/merge-consecutive-stores-nt.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll