clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board

clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board

In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.

The SDIO clock could be also derived from 48Mhz or from sys clock.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>