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(parent: dc694f1) | patch
net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter
authorYevgeny Kliteynik <kliteyn@nvidia.com>
Sat, 6 Feb 2021 20:11:52 +0000 (22:11 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 10 Mar 2021 19:01:59 +0000 (11:01 -0800)
commit84076c4c800d1be77199a139d65b8b136a61422e
tree329ff714ad0ff8d129da485c7b6a46e3a771d732tree | snapshot
parentdc694f11a7593b7fd5aabe15a0e6c8fd2de24ebfcommit | diff
net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter

Fix 32-bit variable shift wrapping in dr_ste_v1_get_miss_addr.

Fixes: a6098129c781 ("net/mlx5: DR, Add STEv1 setters and getters")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c diff | blob | history
Domain: System / Kernel;