R600/SI: Define a schedule model and enable the generic machine scheduler
authorTom Stellard <thomas.stellard@amd.com>
Thu, 29 Jan 2015 16:55:25 +0000 (16:55 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Thu, 29 Jan 2015 16:55:25 +0000 (16:55 +0000)
commit83f0bcef7a3e96d022f8d31fd87c8363fd4f9a00
treef29b52cf36d73c5cdc161b00203816b987f329a5
parente75aa4983c8bb64f63c8742d2e3dc32c6966b74b
R600/SI: Define a schedule model and enable the generic machine scheduler

The schedule model is not complete yet, and could be improved.

llvm-svn: 227461
32 files changed:
llvm/lib/Target/R600/AMDGPUSubtarget.cpp
llvm/lib/Target/R600/AMDGPUSubtarget.h
llvm/lib/Target/R600/SIRegisterInfo.cpp
llvm/lib/Target/R600/SIRegisterInfo.h
llvm/test/CodeGen/R600/address-space.ll
llvm/test/CodeGen/R600/atomic_cmp_swap_local.ll
llvm/test/CodeGen/R600/ctpop.ll
llvm/test/CodeGen/R600/cvt_f32_ubyte.ll
llvm/test/CodeGen/R600/ds_read2st64.ll
llvm/test/CodeGen/R600/fceil64.ll
llvm/test/CodeGen/R600/ffloor.f64.ll
llvm/test/CodeGen/R600/ffloor.ll
llvm/test/CodeGen/R600/fmax3.ll
llvm/test/CodeGen/R600/fmin3.ll
llvm/test/CodeGen/R600/fneg-fabs.f64.ll
llvm/test/CodeGen/R600/ftrunc.f64.ll
llvm/test/CodeGen/R600/imm.ll
llvm/test/CodeGen/R600/llvm.memcpy.ll
llvm/test/CodeGen/R600/llvm.round.f64.ll
llvm/test/CodeGen/R600/llvm.round.ll
llvm/test/CodeGen/R600/local-atomics.ll
llvm/test/CodeGen/R600/local-atomics64.ll
llvm/test/CodeGen/R600/local-memory-two-objects.ll
llvm/test/CodeGen/R600/or.ll
llvm/test/CodeGen/R600/si-triv-disjoint-mem-access.ll
llvm/test/CodeGen/R600/smrd.ll
llvm/test/CodeGen/R600/trunc.ll
llvm/test/CodeGen/R600/udivrem.ll
llvm/test/CodeGen/R600/valu-i1.ll
llvm/test/CodeGen/R600/wait.ll
llvm/test/CodeGen/R600/xor.ll
llvm/test/CodeGen/R600/zero_extend.ll