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(parent: f44a5c7) | patch
Refine and/ior/xor/andn masked patterns for V*HFmode.
authorliuhongt <hongtao.liu@intel.com>
Wed, 6 Apr 2022 06:07:50 +0000 (14:07 +0800)
committerliuhongt <hongtao.liu@intel.com>
Thu, 7 Apr 2022 03:53:43 +0000 (11:53 +0800)
commit83e4f0a77691a29aef6711e5ae008a7bce0a1d49
treed7511071f8e2375fda5a341a3ab2c9bbdf6b1d20tree | snapshot
parentf44a5c700f409b96ba923864158349700628133dcommit | diff
Refine and/ior/xor/andn masked patterns for V*HFmode.

There's no masked vpandw or vpandb, similar for vpxor/vpor/vpandn.

gcc/ChangeLog:

* config/i386/sse.md (<sse2_avx2>_andnot<mode>3_mask):
Removed.
(<sse>_andnot<mode>3<mask_name>): Disable V*HFmode patterns
for mask_applied.
(<code><mode>3<mask_name>): Ditto.
(*<code><mode>3<mask_name>): Ditto.
(VFB_128_256): Adjust condition of V8HF/V16HFmode according to
real instruction.
(VFB_512): Ditto.
(VFB): Ditto.
gcc/config/i386/sse.md diff | blob | history
Domain: System / Toolchain;