ASoC: tlv320aic32x4: Model PLL in CCF

ASoC: tlv320aic32x4: Model PLL in CCF

commit 514b044cba667e4b7c383ec79b42b997e624b91d upstream.

Model and manage the on-board PLL as a component in the Core
Clock Framework.  This should allow us to do some more complex
clock management and power control.  Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.

Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>