clk: renesas: Pass clock rate around as 64bit number internally
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Thu, 31 May 2018 17:06:02 +0000 (19:06 +0200)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Fri, 1 Jun 2018 07:42:13 +0000 (09:42 +0200)
commit8376e0e6f74c5e86a821cb81990f2b9429a364f3
tree17e9764522803d82ccfcf66cfadaabc74d9f9e56
parent15e091828592bf87d09a6e780eb9310628a9d79b
clk: renesas: Pass clock rate around as 64bit number internally

The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
drivers/clk/renesas/clk-rcar-gen3.c