[VTA] VTA Compilation Script for Intel FPGA (#3494)
authorLiangfu Chen <liangfu.chen@harman.com>
Wed, 31 Jul 2019 07:19:54 +0000 (15:19 +0800)
committerThierry Moreau <moreau@uw.edu>
Wed, 31 Jul 2019 07:19:54 +0000 (00:19 -0700)
commit83591aa5a139108976baf3febc7263c6f069ce9c
treec29af4f3e660b7034e5b32dc6b5982ba91a5ad75
parent5968eef2544cc40d3c5ae0a996ec535230ef91b5
[VTA] VTA Compilation Script for Intel FPGA (#3494)

* initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
18 files changed:
docs/vta/install.md
tests/lint/add_asf_header.py
tests/lint/check_file_type.py
vta/config/de10nano_sample.json [new file with mode: 0644]
vta/hardware/chisel/src/main/scala/core/Fetch.scala
vta/hardware/chisel/src/main/scala/interface/axi/AXI.scala
vta/hardware/chisel/src/main/scala/shell/Configs.scala
vta/hardware/chisel/src/main/scala/shell/IntelShell.scala [new file with mode: 0644]
vta/hardware/chisel/src/main/scala/vta/Configs.scala
vta/hardware/intel/Makefile [new file with mode: 0644]
vta/hardware/intel/README.md [new file with mode: 0644]
vta/hardware/intel/scripts/compile_design.tcl [new file with mode: 0644]
vta/hardware/intel/scripts/de10_nano_top.v [new file with mode: 0644]
vta/hardware/intel/scripts/ip/vta/vta_hw.tcl [new file with mode: 0644]
vta/hardware/intel/scripts/set_attrs.py [new file with mode: 0755]
vta/hardware/intel/scripts/set_clocks.sdc [new file with mode: 0644]
vta/hardware/intel/scripts/soc_system.tcl [new file with mode: 0644]
vta/python/vta/pkg_config.py