ARM: 8278/1: sa1100: split irq handling for low GPIOs
authorDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Thu, 15 Jan 2015 01:29:16 +0000 (02:29 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 29 Jan 2015 15:24:46 +0000 (15:24 +0000)
commit83508093f448e929bf55d07dd08246d22b03d753
tree60a1ecb382a012bb5626b556f7c2aa848f7038d0
parent7a8ca0a0c480fedf91bdbadf8b90edd5374ce18b
ARM: 8278/1: sa1100: split irq handling for low GPIOs

Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-sa1100/include/mach/irqs.h
arch/arm/mach-sa1100/irq.c
drivers/gpio/gpio-sa1100.c