Small optimization in LSRA for RMW intrinsics (#42564)
authorEgor Chesakov <Egor.Chesakov@microsoft.com>
Tue, 6 Oct 2020 18:58:34 +0000 (11:58 -0700)
committerGitHub <noreply@github.com>
Tue, 6 Oct 2020 18:58:34 +0000 (11:58 -0700)
commit83449c77c242e1839ea614ffa618f9d5d9581e90
tree9bf9fec79480540aaa1a29e6824c5702c67300e9
parentf099416dc1938863da0d53c2db866d14607e40d5
Small optimization in LSRA for RMW intrinsics (#42564)

RMW intrinsic operands doesn't have to be marked as "delay-free" when they can be assigned the same register as op1Reg (i.e. read-modify-write operand) and one of them is the last use.
src/coreclr/src/jit/lsraarm64.cpp