[AMDGPU] Add v3f16/v3i16 support to SDag
authorSebastian Neubauer <sebastian.neubauer@amd.com>
Thu, 23 Jul 2020 14:59:00 +0000 (16:59 +0200)
committerSebastian Neubauer <sebastian.neubauer@amd.com>
Wed, 16 Sep 2020 15:20:27 +0000 (17:20 +0200)
commit833b3b0d3a2ff4b8243940eef1a960050ec48682
treef7437717db750897d7827d8636c381c88c1713ba
parentcd4615120233c54034b42bafc3d2bcc9f29db63d
[AMDGPU] Add v3f16/v3i16 support to SDag

Fix lowering and instruction selection for v3x16 types
and enable InstCombine to emit them.

This patch only implements it for the selection dag.
GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll and
GlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.

Differential Revision: https://reviews.llvm.org/D84420
21 files changed:
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
llvm/lib/Target/AMDGPU/BUFInstructions.td
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll