Recommit [AArch64] Improve codegen for shifted mask op
authorchenglin.bi <chenglin.bi@linaro.org>
Mon, 7 Nov 2022 09:15:59 +0000 (17:15 +0800)
committerchenglin.bi <chenglin.bi@linaro.org>
Mon, 7 Nov 2022 09:16:35 +0000 (17:16 +0800)
commit83255c4a626df5df539a71fba864c99fcb1cb674
treed42fb1291e883a9214dc9b7346f9ab7da8a09f7a
parenta2620e00ffa232a406de3a1d8634beeda86956fd
Recommit [AArch64] Improve codegen for shifted mask op

The original change compares `APInt` to check the constant is the same or not. But shift amount may have different constant types.
So, this patch change to use `getZExtValue` to compare constant value.

Original comment:
The special case for bit extraction pattern is  `((x >> C) & mask) << C`.
It can be combined to `x & (mask << C)` by return true in isDesirableToCommuteWithShift.

Fix: #56427

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D136014
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/shift-logic.ll