author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Sat, 15 Jan 2022 19:37:34 +0000 (14:37 -0500) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Tue, 18 Jan 2022 19:08:36 +0000 (14:08 -0500) | ||
commit | 82de129ab8f723ba94d0026b54d76b11b2a9e4f9 | |
tree | 5faad9b1501af4433ac826a015166a9c0588bece | tree | snapshot |
parent | ea27adb45b780e32d996d9c85f932a71f3e068ba | commit | diff |
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | diff | blob | history | |
llvm/lib/IR/AutoUpgrade.cpp | diff | blob | history | |
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | diff | blob | history | |
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | diff | blob | history | |
llvm/test/Bitcode/amdgcn-alignbit.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll | [moved from llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignb.ll with 58% similarity] | diff | blob | history |