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(parent: 52c326e) | patch
Adding an A15 specific optimization pass for interactions between S/D/Q registers...
authorSilviu Baranga <silviu.baranga@arm.com>
Fri, 15 Mar 2013 18:28:25 +0000 (18:28 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Fri, 15 Mar 2013 18:28:25 +0000 (18:28 +0000)
commit82dd6ac3bc6b361d26b04ca47dbda24d7c17f06c
tree2ae33049c9dd9a2cae65376c5caf01538337581atree | snapshot
parent52c326ec78bb708cff384600aa695911e6aa8562commit | diff
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.

llvm-svn: 177169
llvm/lib/Target/ARM/A15SDOptimizer.cpp [new file with mode: 0644] blob
llvm/lib/Target/ARM/ARM.h diff | blob | history
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp diff | blob | history
llvm/lib/Target/ARM/ARMTargetMachine.cpp diff | blob | history
llvm/lib/Target/ARM/CMakeLists.txt diff | blob | history
llvm/test/CodeGen/ARM/a15-SD-dep.ll [new file with mode: 0644] blob
Domain: System / Toolchain;