[AArch64] Try to convert vector shift operation into vector add operation
authorJingu Kang <jingu.kang@arm.com>
Thu, 15 Jun 2023 16:19:35 +0000 (17:19 +0100)
committerJingu Kang <jingu.kang@arm.com>
Fri, 16 Jun 2023 16:13:45 +0000 (17:13 +0100)
commit82d330e0e04a55ee95dc93980761545a01543fde
tree2a8e8f9cded0b890c916787242551b6e1e48e50d
parented34cb2cd78143a3ec99a91fe2db79bdb1ddfd85
[AArch64] Try to convert vector shift operation into vector add operation

The vector shift instructions tend to be worse than ADD/SUB on AArch64 cores
so this patch supports tablegen patterns for below simple transformation.

 x << 1 ==> x + x

Differential Revision: https://reviews.llvm.org/D153049
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
llvm/test/CodeGen/AArch64/arm64-vshift.ll
llvm/test/CodeGen/AArch64/rax1.ll
llvm/test/CodeGen/AArch64/shl-to-add.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll