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author	Tim Northover <t.p.northover@gmail.com>
	Thu, 19 Nov 2020 12:32:50 +0000 (12:32 +0000)
committer	Tim Northover <t.p.northover@gmail.com>
	Mon, 17 May 2021 09:48:34 +0000 (10:48 +0100)
commit	82a0e808bb2cddc1ce508c6ae654f8350b082256
tree	2fbecbf136a18c9abb8f6999f8d93d2cb8591254	tree \| snapshot
parent	1d9e8e13dd7b3204fa51ada17d1608bdbd1bed66	commit \| diff

IR/AArch64/X86: add "swifttailcc" calling convention.

Swift's new concurrency features are going to require guaranteed tail calls so
that they don't consume excessive amounts of stack space. This would normally
mean "tailcc", but there are also Swift-specific ABI desires that don't
naturally go along with "tailcc" so this adds another calling convention that's
the combination of "swiftcc" and "tailcc".

Support is added for AArch64 and X86 for now.

34 files changed:

llvm/docs/BitCodeFormat.rst		diff \| blob \| history
llvm/docs/CodeGenerator.rst		diff \| blob \| history
llvm/docs/LangRef.rst		diff \| blob \| history
llvm/include/llvm/AsmParser/LLToken.h		diff \| blob \| history
llvm/include/llvm/IR/CallingConv.h		diff \| blob \| history
llvm/lib/AsmParser/LLLexer.cpp		diff \| blob \| history
llvm/lib/AsmParser/LLParser.cpp		diff \| blob \| history
llvm/lib/CodeGen/Analysis.cpp		diff \| blob \| history
llvm/lib/IR/AsmWriter.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64CallingConvention.td		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ARMISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86CallingConv.td		diff \| blob \| history
llvm/lib/Target/X86/X86FastISel.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86RegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86Subtarget.h		diff \| blob \| history
llvm/test/Bitcode/compatibility.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/swift-async.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/swifttail-async.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/AArch64/swifttail-call.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/AArch64/tail-call.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/tailcc-tail-call.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/swifttail-async-i386.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/swifttail-async.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/swifttail-return.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/X86/tailcall-swifttailcc.ll	[new file with mode: 0644]	blob
llvm/utils/emacs/llvm-mode.el		diff \| blob \| history
llvm/utils/vim/syntax/llvm.vim		diff \| blob \| history

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