ix86: Support V{2, 4}DImode arithmetic right shifts for SSE2+ [PR98856]
authorJakub Jelinek <jakub@redhat.com>
Thu, 13 May 2021 10:14:14 +0000 (12:14 +0200)
committerJakub Jelinek <jakub@redhat.com>
Thu, 13 May 2021 10:16:48 +0000 (12:16 +0200)
commit829c4bea06600ea4201462f91ce6d76ca21fdb35
tree3070e0b55476fcec960b33c2bc3e68ae512853bb
parentf1693741cb2b2db519bb82155a3c0880fd820ea3
ix86: Support V{2, 4}DImode arithmetic right shifts for SSE2+ [PR98856]

As mentioned in the PR, we don't support arithmetic right V2DImode or
V4DImode on x86 without -mavx512vl or -mxop.  The ISAs indeed don't have
{,v}psraq instructions until AVX512VL, but we actually can emulate it quite
easily.
One case is arithmetic >> 63, we can just emit {,v}pxor; {,v}pcmpgt for
that for SSE4.2+, or for SSE2 psrad $31; pshufd $0xf5.
Then arithmetic >> by constant > 32, that can be done with {,v}psrad $31
and {,v}psrad $(cst-32) and two operand permutation,
arithmetic >> 32 can be done as {,v}psrad $31 and permutation of that
and the original operand.  Arithmetic >> by constant < 32 can be done
as {,v}psrad $cst and {,v}psrlq $cst and two operand permutation.
And arithmetic >> by variable scalar amount can be done as
arithmetic >> 63, logical >> by the amount, << by (64 - amount of the
>> 63 result; note that the vector << 64 result in 0) and oring together.

I had to improve the permutation generation so that it actually handles
the needed permutations (or handles them better).

2021-05-13  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/98856
* config/i386/i386.c (ix86_shift_rotate_cost): Add CODE argument.
Expect V2DI and V4DI arithmetic right shifts to be emulated.
(ix86_rtx_costs, ix86_add_stmt_cost): Adjust ix86_shift_rotate_cost
caller.
* config/i386/i386-expand.c (expand_vec_perm_2perm_interleave,
expand_vec_perm_2perm_pblendv): New functions.
(ix86_expand_vec_perm_const_1): Use them.
* config/i386/sse.md (ashr<mode>3<mask_name>): Rename to ...
(<mask_codefor>ashr<mode>3<mask_name>): ... this.
(ashr<mode>3): New define_expand with VI248_AVX512BW iterator.
(ashrv4di3): New define_expand.
(ashrv2di3): Change condition to TARGET_SSE2, handle !TARGET_XOP
and !TARGET_AVX512VL expansion.

* gcc.target/i386/sse2-psraq-1.c: New test.
* gcc.target/i386/sse4_2-psraq-1.c: New test.
* gcc.target/i386/avx-psraq-1.c: New test.
* gcc.target/i386/avx2-psraq-1.c: New test.
* gcc.target/i386/avx-pr82370.c: Adjust expected number of vpsrad
instructions.
* gcc.target/i386/avx2-pr82370.c: Likewise.
* gcc.target/i386/avx512f-pr82370.c: Likewise.
* gcc.target/i386/avx512bw-pr82370.c: Likewise.
* gcc.dg/torture/vshuf-4.inc: Add two further permutations.
* gcc.dg/torture/vshuf-8.inc: Likewise.
13 files changed:
gcc/config/i386/i386-expand.c
gcc/config/i386/i386.c
gcc/config/i386/sse.md
gcc/testsuite/gcc.dg/torture/vshuf-4.inc
gcc/testsuite/gcc.dg/torture/vshuf-8.inc
gcc/testsuite/gcc.target/i386/avx-pr82370.c
gcc/testsuite/gcc.target/i386/avx-psraq-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx2-pr82370.c
gcc/testsuite/gcc.target/i386/avx2-psraq-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx512bw-pr82370.c
gcc/testsuite/gcc.target/i386/avx512f-pr82370.c
gcc/testsuite/gcc.target/i386/sse2-psraq-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/sse4_2-psraq-1.c [new file with mode: 0644]