[RISCV] Match neg (and x, 1) to two shifts to improve codesize
authorPhilip Reames <preames@rivosinc.com>
Mon, 19 Dec 2022 21:56:01 +0000 (13:56 -0800)
committerPhilip Reames <listmail@philipreames.com>
Mon, 19 Dec 2022 22:17:26 +0000 (14:17 -0800)
commit828b1c55cb7f5b327ea7399bc6f6386ecad14972
treecd4528c9ac386c885ba512db19425cc7140a9bfa
parent30199d11d27460e8c96a81c493526c32dbea428d
[RISCV] Match neg (and x, 1) to two shifts to improve codesize

The negate operation is never compressible (as the destination and rs1 register must differ). The two shift versions will be equal size if the input GPR is reused, or smaller if this is the only use of the input.

For clarity, the operation being performed is (select (low-bit-of x), -1, 0).

Differential Revision: https://reviews.llvm.org/D140319
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/pr58511.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
llvm/test/CodeGen/RISCV/select.ll
llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll